1. Field of the Invention
The present invention relates to a method for inhibiting a void caused in a junction when a printed circuit board is manufactured, and to a structure of the printed circuit board.
2. Description of the Related Art
In recent years, as electronic equipment become miniaturized, a printed circuit board to be incorporated therein is required to be more miniaturized and thinner. In order to realize such miniaturization, miniaturizing and thinning of a semiconductor package to be mounted on a printed wiring board are pursued. As a semiconductor package that can realize both miniaturization and higher functionality, a ball grid array (BGA), a chip size package (CSP), or a land grid array (LGA) is used in which a plurality of connection terminals can be arranged on a lower surface of the semiconductor package.
When such a semiconductor package is mounted on a printed wiring board, by heating and melting solder paste in a reflow furnace, an electrode pad of the semiconductor package and an electrode pad of the printed wiring board are joined to each other. In general, solder paste contains flux, which has the function of removing a surface oxide film of a solder particle and adjusting viscosity thereof. However, when solder paste is heated, there is a problem in that a solvent and an activator contained in the flux are gasified to leave a void in a solidified solder junction.
In a manufacturing method disclosed in Japanese Patent Application Laid-Open No. 2004-55827, first, as illustrated in FIG. 12A, solder paste 8 is supplied to an electrode pad 4 provided on a printed wiring board 101. The manufacturing method has a feature in that, in this step, the solder paste 8 is supplied to a position offset from the electrode pad 4. Specifically, the solder paste 8 is supplied so as to extend both on the electrode pad 4 and on a solder resist 11.
As a related art for reducing a void caused in the junction, in Japanese Patent Application Laid-Open No. 2004-55827, there is proposed a manufacturing method involving connecting pin-like connection terminals to a printed wiring board.
The printed wiring board used in Japanese Patent Application Laid-Open No. 2004-55827 has a structure in which, as illustrated in FIG. 12A, the electrode pad 4 is formed on a surface of the printed wiring board 101 and an outer edge portion of the electrode pad 4 is covered with the solder resist 11. As the electrode pad 4, copper that has good wettability with the solder serving as a joining material and exhibits good conductivity is used. On the other hand, as the solder resist 11, a resin that has poor wettability with the solder and has insulation properties is used.
Then, as illustrated in FIG. 12B, a pin-like terminal component 100 is mounted so as to be aligned with the electrode pad 4 on the printed wiring board 101. The connection terminal provided on a lower portion of the pin-like terminal component 100 has the same size as that of the electrode pad 4. Therefore, in a step of mounting the pin-like terminal component 100, the solder paste 8 supplied onto the electrode pad 4 is pressed by the pin-like terminal component 100, but a portion of the solder paste 8 that is supplied so as to be offset from the electrode pad 4 is not pressed.
Then, as illustrated in FIG. 12C, by heating and melting the solder with a furnace, the pin-like terminal component 100 and the printed wiring board 101 are joined to each other. In this step, the portion of the solder paste 8 that is supplied so as to be offset from the electrode pad 4 agglomerates as one mass, when molten by heat, and moves so as to spread on the entire electrode pad 4. When the flux in the solder paste 8 removes a surface oxide film of the electrode pad 4, gas is generated. However, the movement of the molten solder forces the gas out of the solder. By solidifying the molten solder through cooling under a state in which the gas is forced out, a void caused in a solder junction 10 can be reduced as illustrated in FIG. 12D.
In recent years, because a solder ball is not formed on the electrode pad, an LGA is adopted when a thinner semiconductor package is required or when repeated heat application is not permitted in mounting as in the case of a CCD or a CMOS. When the LGA is mounted, a gap between the semiconductor package and the printed wiring board is small. Therefore, an area of the solder junction exposed to outside air is small and the generated gas is less likely to escape to the outside, and thus, a large void is more liable to be caused. When a void is caused in the solder junction, a junction area joined by the solder becomes smaller to lower joining reliability. As a joint pitch becomes smaller and as the junction becomes smaller as in recent years, the lowered reliability due to the void becomes a severe problem.
The above-mentioned manufacturing method disclosed in Japanese Patent Application Laid-Open No. 2004-55827 has been proposed for the purpose of reducing a void caused in a junction between a pin-like connection terminal for a pin grid array (PGA) package and an electrode pad. Therefore, when the related art is applied to a case in which not a pin-like connection terminal but a semiconductor package such as an LGA is joined to a printed wiring board, a phenomenon occurs in which solder supplied so as to be offset cannot move to a connection terminal of the printed wiring board and is separated.
When the molten solder is separated and moves between electrode pads, adjacent electrode pads may be connected to each other to cause a short circuit failure. Further, the separation of the solder reduces a volume of solder that remains on the electrode pad to lower the joining reliability. Further, when the gap between the semiconductor package and the printed wiring board is small, the flux contained in the solder paste may extend beyond the electrode pad due to capillary action. When the flux remains between adjacent electrode pads as a residue, another problem arises in that an insulation resistance between the adjacent electrode pads is lowered under the influence of the activator in the flux.